Regviz

NXP Semiconductors /LPC408x_7x /SYSCON /MATRIXARB

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MATRIXARB

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/NeoM3/SYSCON/MATRIXARB#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PRI_ICODE 0PRI_DCODE 0PRI_SYS 0PRI_GPDMA 0PRI_ETH 0PRI_LCD 0PRI_USB 0RESERVED 0 (ROM_LAT)ROM_LAT 0RESERVED

Description

Matrix arbitration register

Fields

PRI_ICODE

I-Code bus priority. Should be lower than PRI_DCODE for proper operation.
PRI_DCODE

D-Code bus priority.
PRI_SYS

System bus priority.
PRI_GPDMA

General Purpose DMA controller priority.
PRI_ETH

Ethernet DMA priority.
PRI_LCD

LCD DMA priority.
PRI_USB

USB DMA priority.
RESERVED

Reserved. Read value is undefined, only zero should be written.
ROM_LAT

ROM latency select. Should always be 0.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data